[all-commits] [llvm/llvm-project] d1baed: [DAG] select Cond, -1, C --> or (sext Cond), C if ...

[deadalnix via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d1baed7c9c8341c43c696cce1b7ec846c21b0b45
      https://github.com/llvm/llvm-project/commit/d1baed7c9c8341c43c696cce1b7ec846c21b0b45
  Author: Amaury Séchet <deadalnix at gmail.com>
  Date:   2022-09-27 (Tue, 27 Sep 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/PowerPC/crbits.ll
    M llvm/test/CodeGen/PowerPC/prefer-dqform.ll
    M llvm/test/CodeGen/X86/memcmp-more-load-pairs-x32.ll
    M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
    M llvm/test/CodeGen/X86/memcmp-optsize-x32.ll
    M llvm/test/CodeGen/X86/memcmp-optsize.ll
    M llvm/test/CodeGen/X86/memcmp-pgso-x32.ll
    M llvm/test/CodeGen/X86/memcmp-pgso.ll
    M llvm/test/CodeGen/X86/memcmp-x32.ll
    M llvm/test/CodeGen/X86/memcmp.ll
    M llvm/test/CodeGen/X86/midpoint-int.ll
    M llvm/test/CodeGen/X86/select.ll
    M llvm/test/CodeGen/X86/select_const.ll

  Log Message:
  -----------
  [DAG] select Cond, -1, C --> or (sext Cond), C if Cond is MVT::i1

This seems to be beneficial overall, except for midpoint-int.ll .

The X86 backend seems to generate zeroing that are not necesary.

Reviewed By: shchenz

Differential Revision: https://reviews.llvm.org/D131260