[all-commits] [llvm/llvm-project] afdd60: [LegalizeTypes][RISCV] Support f16 in ExpandIntRes...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: afdd600a491df2c951dc1aa341153cc9222ea07b
      https://github.com/llvm/llvm-project/commit/afdd600a491df2c951dc1aa341153cc9222ea07b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-09-26 (Mon, 26 Sep 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
    R llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics-strict.ll
    M llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll

  Log Message:
  -----------
  [LegalizeTypes][RISCV] Support f16 in ExpandIntRes_LLROUND_LLRINT.

Promote f16 to f32 and use the f32 libcall.

I deleted rv64zfh-half-intrinsics-strict.ll because it only existed due to this issue breaking rv32.

Differential Revision: https://reviews.llvm.org/D134579