[all-commits] [llvm/llvm-project] e5e3dc: [mlgo] Add in-development instruction based featur...

[Aiden Grossman via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e5e3dccd0741c2cf6e1885f0b6053fcfc6684102
      https://github.com/llvm/llvm-project/commit/e5e3dccd0741c2cf6e1885f0b6053fcfc6684102
  Author: Aiden Grossman <agrossman154 at yahoo.com>
  Date:   2022-09-17 (Sat, 17 Sep 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/SlotIndexes.h
    M llvm/lib/CodeGen/MLRegallocEvictAdvisor.cpp
    A llvm/lib/CodeGen/MLRegallocEvictAdvisor.h
    A llvm/test/CodeGen/MLRegalloc/dev-mode-extra-features-logging.ll
    M llvm/unittests/CodeGen/CMakeLists.txt
    A llvm/unittests/CodeGen/MLRegallocDevelopmentFeatures.cpp

  Log Message:
  -----------
  [mlgo] Add in-development instruction based features for regalloc advisor

This patch adds in instruction based features to the regalloc advisor
gated behind a flag so a user can decide at runtime whether or not they
want to enable the feature. The features are only enabled when LLVM is
compiled in MLGO develpment mode (LLVM_HAVE_TF_API) is set to true.

To extract the instruction features, I'm taking a list of segments from
each LiveInterval and noting the start and end SlotIndices. This list is then
sorted based on the start SlotIndex and I iterate through each SlotIndex
to grab instructions, making sure to check for overlaps. This results in
a vector of opcodes and binary mapping matrix that maps live ranges to the
opcodes of the instructions within that LR.

Reviewed By: mtrofin

Differential Revision: https://reviews.llvm.org/D131930