[all-commits] [llvm/llvm-project] e438f2: [DAGCombine] Do not fold SRA/SRL of MUL into MULH ...

[Juan Manuel Martinez Caamaño via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e438f2d821119439c2b05b2fef7617064a6233bc
      https://github.com/llvm/llvm-project/commit/e438f2d821119439c2b05b2fef7617064a6233bc
  Author: Juan Manuel MARTINEZ CAAMAÑO <juamarti at amd.com>
  Date:   2022-09-16 (Fri, 16 Sep 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    A llvm/test/CodeGen/AMDGPU/dagcomb-mullohi.ll

  Log Message:
  -----------
  [DAGCombine] Do not fold SRA/SRL of MUL into MULH when MUL's LSB are
used, and MUL_LOHI is available

Folding into a sra(mul) / srl(mul) into a mulh introduces an extra
multiplication to compute the high half of the multiplication,
while it is more profitable to compute the high and lower halfs with a
single mul_lohi.

Differential Revision: https://reviews.llvm.org/D133768