[all-commits] [llvm/llvm-project] 0a1455: [RISCV] Fix a silent miscompile in copyPhysReg

Philip Reames via All-commits all-commits at lists.llvm.org
Wed Sep 14 14:46:04 PDT 2022


  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0a145516a24bdda0440754adc162649f788ba673
      https://github.com/llvm/llvm-project/commit/0a145516a24bdda0440754adc162649f788ba673
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [RISCV] Fix a silent miscompile in copyPhysReg

Found this when adding verifier rules. The case which arises is that we have a DefMBBI which has a VecPolicy operand. The code was not expecting this, and the unconditional copy of the last two operands resulted in the SEW and VecPolicy fields being added to the VMV_V_V as AVL and SEW respectively.

Oddly, this appears to be a silent in practice. There's no test change despite verifier changes proving that we definitely hit this in existing tests.

Differential Revision: https://reviews.llvm.org/D133868


  Commit: e395915ac01ffd9b6cf743f361df7265f319a8c7
      https://github.com/llvm/llvm-project/commit/e395915ac01ffd9b6cf743f361df7265f319a8c7
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2022-09-14 (Wed, 14 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [RISCV] Verify SEW/VecPolicy immediate values

Copy the asserts from the printing code, and turn them into actual verifier rules. Doing this revealed an existing bug - see 0a14551.

Differential Revision: https://reviews.llvm.org/D133869


Compare: https://github.com/llvm/llvm-project/compare/cb21b7d274e9...e395915ac01f


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