[all-commits] [llvm/llvm-project] 5224ba: [RISCV] Fix a bug in i32 FP_TO_UINT_SAT lowering o...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5224bae6130722dd41561422df1133eab60eb969
      https://github.com/llvm/llvm-project/commit/5224bae6130722dd41561422df1133eab60eb969
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-convert.ll
    M llvm/test/CodeGen/RISCV/float-convert.ll
    M llvm/test/CodeGen/RISCV/half-convert.ll

  Log Message:
  -----------
  [RISCV] Fix a bug in i32 FP_TO_UINT_SAT lowering on RV64.

We use the saturating behavior of fcvt.wu.h/s/d but forgot to
take into account that fcvt.wu will sign extend the saturated
result. According to computeKnownBits a promoted FP_TO_UINT_SAT
is expected to zero extend the saturated value.

In many case the upper bits aren't be demanded so this wouldn't
be an issue. But if we computeKnownBits caused an AND to be removed
it would be a bug.

This patch inserts an AND during to zero the upper bits.

Unfortunately, this pessimizes code if we aren't able to tell if
the upper bits are demanded. To fix that we could custom type
promote the FP_TO_UINT_SAT with SEXT_INREG after it, but I'll
leave that for future work.

I haven't found a failure from this, I was revisiting the code to
add vector support and spotted it.

Differential Revision: https://reviews.llvm.org/D133746