[all-commits] [llvm/llvm-project] 5fcb5d: [RISCV] Add assertion of hasVecPolicyOp to catch m...

[Yeting Kuo via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5fcb5d77599e2b028dd8b7b8a3a7853701838e0c
      https://github.com/llvm/llvm-project/commit/5fcb5d77599e2b028dd8b7b8a3a7853701838e0c
  Author: Yeting Kuo <yeting.kuo at sifive.com>
  Date:   2022-09-13 (Tue, 13 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

  Log Message:
  -----------
  [RISCV] Add assertion of hasVecPolicyOp to catch masked intrinsic without policy operand.

The original code may have incorrect result if there is a masked instruction
without policy operand to make us set its policy to TUMU. The patch adds an
assertion to catch the instruction.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D133302