[all-commits] [llvm/llvm-project] 4186a4: [RISCV] Custom type legalize i32 loads by sign ext...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4186a49d793eb69afee7a724dad87a8ecd434e51
      https://github.com/llvm/llvm-project/commit/4186a49d793eb69afee7a724dad87a8ecd434e51
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-09-12 (Mon, 12 Sep 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/sextw-removal.ll
    M llvm/test/CodeGen/RISCV/vec3-setcc-crash.ll

  Log Message:
  -----------
  [RISCV] Custom type legalize i32 loads by sign extending.

The default is to use extload which can become a zextload or
sextload if it is followed by an 'and' or sext_inreg.

Sometimes type legalization will introduce an 'and' from promoting
something like 'srl X, C' and a sext_inreg from from a setcc. The
'and' could be freely folded with the promoted 'srl' by using srliw,
but the sext_inreg can't be folded into a compare. DAG combiner
will see both of these choices and may decide to fold the 'and'
instead of the 'sext_inreg'. This forces the sext_inreg to become
a sext.w.

By picking sextload in the type legalizer we take this choice away.
Looking at spec2006 compiled with Zba and Zbb this appeared to be
net reduction in lines of code in the objdump disassembly output.

This is similar to what we do with i32 add/sub/mul/shl in
type legalization where we always emit a sext_inreg.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D130397