[all-commits] [llvm/llvm-project] 783419: TableGen: Introduce generated getSubRegisterClass ...

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 78341948370b56cd98c0b70dd9c51612b97d7621
      https://github.com/llvm/llvm-project/commit/78341948370b56cd98c0b70dd9c51612b97d7621
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-09-12 (Mon, 12 Sep 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp
    M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.h
    M llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  TableGen: Introduce generated getSubRegisterClass function

Currently there isn't a generic way to get a smaller register class
that can be produced from a subregister of a larger class. Replaces a
manually implemented version for AMDGPU. This will be used to improve
subregister support in the allocator.