[all-commits] [llvm/llvm-project] 41a3b5: [RISCV] Teach combineDeMorganOfBoolean to handle (...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 41a3b5739b944076402a9eb670b08d3e34f3f394
      https://github.com/llvm/llvm-project/commit/41a3b5739b944076402a9eb670b08d3e34f3f394
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-25 (Thu, 25 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/double-previous-failure.ll
    M llvm/test/CodeGen/RISCV/setcc-logic.ll

  Log Message:
  -----------
  [RISCV] Teach combineDeMorganOfBoolean to handle (and (xor X, 1), (not Y)).

SimplifyDemandedBits tries to agressively turn xor immediates into -1
to match a 'not' instruction. In this case, because X is a boolean, the
upper bits of (xor X, 1) are known to be 0. Because this is an AND
instruction, that means those bits aren't demanded from the other
operand, and thus SimplifyDemandedBits can turn (xor Y, 1) to (not Y).

We need to detect that this has happened to enable the DeMorgan
optimization. To do this we allow one of the xors to use -1 when
the outer operation is And.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132671