[all-commits] [llvm/llvm-project] ec91d7: [RISCV] Apply DeMorgan's law to (and/or (xor X, 1)...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ec91d761ac03378456fe0528e0fe8ea4dd70927c
      https://github.com/llvm/llvm-project/commit/ec91d761ac03378456fe0528e0fe8ea4dd70927c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-25 (Thu, 25 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/setcc-logic.ll

  Log Message:
  -----------
  [RISCV] Apply DeMorgan's law to (and/or (xor X, 1), (xor Y, 1)) if X and Y are 0/1.

This optimizes xors that appear due to legalizing setge/setle which
require an xor with 1. This reduces the number of xors and may
allow the xor to fold with a beqz or bnez.

Differential Revision: https://reviews.llvm.org/D132614