[all-commits] [llvm/llvm-project] 30b045: [AArch64][SVE] Extend LD1RQ ISel patterns to cover...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 30b045aba603e61239ff121de908597c536d2c8e
      https://github.com/llvm/llvm-project/commit/30b045aba603e61239ff121de908597c536d2c8e
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2022-08-25 (Thu, 25 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads.ll
    M llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s
    M llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-sve-instructions.s

  Log Message:
  -----------
  [AArch64][SVE] Extend LD1RQ ISel patterns to cover missing addressing modes

Add some missing patterns for ld1rq's scalar + scalar addressing mode.
Also, adds the scalar + imm and scalar + scalar addressing modes for
the patterns added in https://reviews.llvm.org/D130010

Differential Revision: https://reviews.llvm.org/D130993