[all-commits] [llvm/llvm-project] f9de13: [X86] Promote i8/i16 CTTZ (BSF) instructions and r...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f9de13232f9b1e8f35625a3a4af4c529ebc7663d
      https://github.com/llvm/llvm-project/commit/f9de13232f9b1e8f35625a3a4af4c529ebc7663d
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-08-24 (Wed, 24 Aug 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/BasicTTIImpl.h
    M llvm/include/llvm/CodeGen/TargetLowering.h
    M llvm/lib/CodeGen/CodeGenPrepare.cpp
    M llvm/lib/Target/AArch64/AArch64ISelLowering.h
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
    M llvm/lib/Target/ARM/ARMISelLowering.cpp
    M llvm/lib/Target/ARM/ARMISelLowering.h
    M llvm/lib/Target/Hexagon/HexagonISelLowering.h
    M llvm/lib/Target/Mips/MipsISelLowering.cpp
    M llvm/lib/Target/Mips/MipsISelLowering.h
    M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
    M llvm/lib/Target/PowerPC/PPCISelLowering.h
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/SystemZ/SystemZISelLowering.h
    M llvm/lib/Target/VE/VEISelLowering.h
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
    M llvm/lib/Target/WebAssembly/WebAssemblyISelLowering.h
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/lib/Target/X86/X86ISelLowering.h
    M llvm/test/Analysis/CostModel/X86/cttz.ll
    M llvm/test/CodeGen/X86/clz.ll

  Log Message:
  -----------
  [X86] Promote i8/i16 CTTZ (BSF) instructions and remove speculation branch

This patch adds a Type operand to the TLI isCheapToSpeculateCttz/isCheapToSpeculateCtlz callbacks, allowing targets to decide whether branches should occur on a type-by-type/legality basis.

For X86, this patch proposes to allow CTTZ speculation for i8/i16 types that will lower to promoted i32 BSF instructions by masking the operand above the msb (we already do something similar for i8/i16 TZCNT). This required a minor tweak to CTTZ lowering - if the src operand is known never zero (i.e. due to the promotion masking) we can remove the CMOV zero src handling.

Although BSF isn't very fast, most CPUs from the last 20 years don't do that bad a job with it, although there are some annoying passthrough EFLAGS dependencies. Additionally, now that we emit 'REP BSF' in most cases, we are tending towards assuming this will most likely be executed as a TZCNT instruction on any semi-modern CPU.

Differential Revision: https://reviews.llvm.org/D132520