[all-commits] [llvm/llvm-project] 8b24e6: [InstCombine] Add tests for D130075

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8b24e64014efcef3ab56a98ea262cc0c01a03628
      https://github.com/llvm/llvm-project/commit/8b24e64014efcef3ab56a98ea262cc0c01a03628
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-08-22 (Mon, 22 Aug 2022)

  Changed paths:
    M llvm/test/Transforms/InstCombine/add2.ll

  Log Message:
  -----------
  [InstCombine] Add tests for D130075

Differential Revision: https://reviews.llvm.org/D132381


  Commit: 2754ff883d9ebf5452a10a2b739262b481cb3458
      https://github.com/llvm/llvm-project/commit/2754ff883d9ebf5452a10a2b739262b481cb3458
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-08-22 (Mon, 22 Aug 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
    M llvm/test/Transforms/InstCombine/add2.ll
    M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
    M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll

  Log Message:
  -----------
  [InstCombine] Try not to demand low order bits for Add

Don't demand low order bits from the LHS of an Add if:
- they are not demanded in the result, and
- they are known to be zero in the RHS, so they can't possibly
  overflow and affect higher bit positions

This is intended to avoid a regression from a future patch to change
the order of canonicalization of ADD and AND.

Differential Revision: https://reviews.llvm.org/D130075


  Commit: f82c55fa082711f520a7359393b483956b69bf08
      https://github.com/llvm/llvm-project/commit/f82c55fa082711f520a7359393b483956b69bf08
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-08-22 (Mon, 22 Aug 2022)

  Changed paths:
    M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
    M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
    M llvm/test/Transforms/InstCombine/add.ll
    M llvm/test/Transforms/InstCombine/integer-round-up-pow2-alignment.ll
    M llvm/test/Transforms/InstCombine/or.ll
    M llvm/test/Transforms/InstCombine/sub.ll

  Log Message:
  -----------
  [InstCombine] Change order of canonicalization of ADD and AND

Canonicalize ((x + C1) & C2) --> ((x & C2) + C1) for suitable constants
C1 and C2, instead of the other way round. This should allow more
constant ADDs to be matched as part of addressing modes for loads and
stores.

Differential Revision: https://reviews.llvm.org/D130080


Compare: https://github.com/llvm/llvm-project/compare/d848186a3bee...f82c55fa0827