[all-commits] [llvm/llvm-project] 961838: [RISCV] Add passthru operand to RISCVISD::SETCC_VL.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 961838cc132faba9330364f2e5bdeae673454c9f
      https://github.com/llvm/llvm-project/commit/961838cc132faba9330364f2e5bdeae673454c9f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-19 (Fri, 19 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

  Log Message:
  -----------
  [RISCV] Add passthru operand to RISCVISD::SETCC_VL.

Use it to the fix a bug in the fceil/ffloor lowerings. We were
setting the passthru to IMPLICIT_DEF before and using a mask
agnostic policy. This means where the incoming bits in
the mask were 0 they could be anything in the outgoing mask. We
want those bits in the outgoing mask to be 0. This means we need to
pass the input mask as the passthru.

This generates worse code because we are unable to allocate the
v0 register to the output due to an earlyclobber constraint. We
probably need a special TIED pseudoinstruction and probably custom
isel since you can't use V0 twice in the input pattern.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132058