[all-commits] [llvm/llvm-project] c9a41f: [RISCV] Prefer vnsrl.wi v8, v8, 0 over vnsrl.wx v8...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c9a41fe60ab62f7a40049c100adcc8087a47669b
      https://github.com/llvm/llvm-project/commit/c9a41fe60ab62f7a40049c100adcc8087a47669b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-19 (Fri, 19 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/fpclamptosat_vec.ll
    M llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fptosi-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/fptoui-sat.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptosi-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoui-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vtrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll

  Log Message:
  -----------
  [RISCV] Prefer vnsrl.wi v8, v8, 0 over vnsrl.wx v8, v8, x0.

I have a couple data points that some microarchitectures prefer
the immediate 0 over x0. Does anyone know of microarchitectures
where the opposite is true?

Unfortunately, this is different than the vncvt.x.x.w alias
from the spec. Perhaps the alias was poorly chosen if x0 isn't
as optimal as immediate 0 on all microarchitectures.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D132041