[all-commits] [llvm/llvm-project] 3f5619: [AArch64] Fix and add A64FX scheduling resource/la...

[ytmukai via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3f561996bf7193091bc6670a2e7804b0cb0bb936
      https://github.com/llvm/llvm-project/commit/3f561996bf7193091bc6670a2e7804b0cb0bb936
  Author: Yuta Mukai <mukai.yuta at fujitsu.com>
  Date:   2022-08-09 (Tue, 09 Aug 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA64FX.td
    A llvm/test/tools/llvm-mca/AArch64/A64FX/A64-basic-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-neon-instructions.s
    A llvm/test/tools/llvm-mca/AArch64/A64FX/A64FX-sve-instructions.s

  Log Message:
  -----------
  [AArch64] Fix and add A64FX scheduling resource/latency info

1. Missing instruction information (FTSSEL, FMSB, PFIRST and RDFFR)
   is added and CompleteModel is set to one.

2. Information for pseudo SVE instructions is added. Those
   instructions are present at the time of scheduling.

3. Resource and latency information for SVE instructions is modified
   to be more accurate.
   For example, the description for CMPEQ, which consumes one cycle
   each of unit FLA and PPR, is as follows.
```
Previous:
  def A64FXGI01 : ProcResGroup<[A64FXIPFLA, A64FXIPPR]>;
  def A64FXWrite_4Cyc_GI01 : SchedWriteRes<[A64FXGI01]> {...
Modified:
  def A64FXGI0 : ProcResGroup<[A64FXIPFLA]>;
  def A64FXGI1 : ProcResGroup<[A64FXIPPR]>;
  def A64FXWrite_CMP : SchedWriteRes<[A64FXGI0, A64FXGI1]> {...
```

Reference: A64FX Microarchitecture Manual (Table 16-3)
https://github.com/fujitsu/A64FX/blob/master/doc/A64FX_Microarchitecture_Manual_en_1.7.pdf

Reviewed By: dmgreen, kawashima-fj

Differential Revision: https://reviews.llvm.org/D131165