[all-commits] [llvm/llvm-project] c1f65d: [flang] Add an explicit condition for the BITS=0 c...

[Tarun Prabhu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c1f65df19c0f7324db8a7ec235308aee55fe22ef
      https://github.com/llvm/llvm-project/commit/c1f65df19c0f7324db8a7ec235308aee55fe22ef
  Author: Tarun Prabhu <tarun at lanl.gov>
  Date:   2022-08-08 (Mon, 08 Aug 2022)

  Changed paths:
    M flang/lib/Lower/IntrinsicCall.cpp
    M flang/test/Lower/Intrinsics/maskl.f90
    M flang/test/Lower/Intrinsics/maskr.f90

  Log Message:
  -----------
  [flang] Add an explicit condition for the BITS=0 case in the MASKL and MASKR intrinsics.

This fixes issue #56706.

Differential Revision: https://reviews.llvm.org/D130590