[all-commits] [llvm/llvm-project] e2bfbe: [RISCV] Add ReadFStoreData as a SchedRead.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e2bfbed2bb647dc95d3f7e66d07dad0db1cb36b9
      https://github.com/llvm/llvm-project/commit/e2bfbed2bb647dc95d3f7e66d07dad0db1cb36b9
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-08-08 (Mon, 08 Aug 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVSchedRocket.td
    M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
    M llvm/lib/Target/RISCV/RISCVSchedule.td

  Log Message:
  -----------
  [RISCV] Add ReadFStoreData as a SchedRead.

The floating point stores use a different register class, it
probably makes sense to have a different SchedRead.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D131379