[all-commits] [llvm/llvm-project] e0fbd9: [AArch64][SVE] Add ISel pattern to lower DUPLANE12...

[Matthew Devereau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e0fbd990c9cb367a3820fc788d18d9859d9380fc
      https://github.com/llvm/llvm-project/commit/e0fbd990c9cb367a3820fc788d18d9859d9380fc
  Author: Matt Devereau <matthew.devereau at arm.com>
  Date:   2022-07-21 (Thu, 21 Jul 2022)

  Changed paths:
    M llvm/include/llvm/Target/TargetSelectionDAG.td
    M llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
    M llvm/test/CodeGen/AArch64/sve-intrinsics-perm-select.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.ll

  Log Message:
  -----------
  [AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD

Following on from https://reviews.llvm.org/D128902, lower DUPLANE128 to LD1RQD
for integer load types from instruction selection.

Differential Revision: https://reviews.llvm.org/D130010