[all-commits] [llvm/llvm-project] 3b3349: [RISCV] Add a test showing a miscompilation with s...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3b334978d565bf39c80b6b81e459bd33d204e2a3
      https://github.com/llvm/llvm-project/commit/3b334978d565bf39c80b6b81e459bd33d204e2a3
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    A llvm/test/CodeGen/RISCV/rvv/vrgatherei16-subreg-liveness.ll

  Log Message:
  -----------
  [RISCV] Add a test showing a miscompilation with subreg liveness

This patch adds a test which shows that we may incorrectly register
allocate for RVV instructions which have no-overlap constraints on
source/dest registers of different LMUL groups.

The particular case shows that a vrgatherei16 instruction writes to a
LMUL=1 register group v11 and reads from an EMUL=2 register group
v10/v11. This breaks the overlap constraints of the vrgatherei16
instruction.

The test also shows that disabling subregister liveness fixes the test.

We use `early-clobber` on the `VR` dest and the `VRM2` source to enforce
the constraint but with subregister liveness this constraint is not met.

It's unclear to me at this point whether this is per-design of
early-clobber in conjunction with subregisters (meaning we should find
another way of expressing this constraint) or whether it's a bug in the
register allocator somewhere.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D129639