[all-commits] [llvm/llvm-project] a2fe6a: [NFC][SVE] Add tests for zext(cmpeq(x, splat(0)))

[Cullen Rhodes via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a2fe6aa9ebf38fd1b45e8514325e6e40400c15ff
      https://github.com/llvm/llvm-project/commit/a2fe6aa9ebf38fd1b45e8514325e6e40400c15ff
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/sve-cmp-folds.ll

  Log Message:
  -----------
  [NFC][SVE] Add tests for zext(cmpeq(x, splat(0)))

In preparation for follow up patch folding above to CNOT.

Reviewed By: paulwalker-arm, peterwaller-arm

Differential Revision: https://reviews.llvm.org/D129625


  Commit: 055b409cea9f0672595e6a17446cb4d770f10bc8
      https://github.com/llvm/llvm-project/commit/055b409cea9f0672595e6a17446cb4d770f10bc8
  Author: Cullen Rhodes <cullen.rhodes at arm.com>
  Date:   2022-07-14 (Thu, 14 Jul 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SchedA57.td

  Log Message:
  -----------
  [AArch64][NFC] Drop 'V' from ASIMD FP convert, other, D/Q-form regex

In the Cortex A57 Optimization Guide [1] VCVTAU (AArch32) is incorrectly
listed in the AArch64 instructions for instruction groups:

  - ASIMD FP convert, other, D-form
  - ASIMD FP convert, other, Q-form

It's meant to be FCVTAU, this will be fixed in future releases of the guide.

[1] https://developer.arm.com/documentation/uan0015/b


Compare: https://github.com/llvm/llvm-project/compare/9b87ad33c1fa...055b409cea9f