[all-commits] [llvm/llvm-project] b2e968: [RISCV] isel (shl (and X, C2), C) -> (slli (srliw ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b2e9684fe4d10dbdd7679a29c6f971dc59ede3dd
      https://github.com/llvm/llvm-project/commit/b2e9684fe4d10dbdd7679a29c6f971dc59ede3dd
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-07-02 (Sat, 02 Jul 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    M llvm/test/CodeGen/RISCV/rv64zba.ll

  Log Message:
  -----------
  [RISCV] isel (shl (and X, C2), C) -> (slli (srliw X, C3), C3+C).

where C2 has 32 leading zeros and C3 trailing zeros.

When the shl is used by an add C is 1,2 or 3, we end up matching
(add (shl X, C), Y) first. This leaves an and with a constant that
is harder to materialize.