[all-commits] [llvm/llvm-project] 370bee: [clang-format] Fix whitespace counting stuff
eywdck2l via All-commits
all-commits at lists.llvm.org
Sat Jun 25 19:21:49 PDT 2022
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 370bee480139bd37fe8c0c8c03ecd19ed9223f01
https://github.com/llvm/llvm-project/commit/370bee480139bd37fe8c0c8c03ecd19ed9223f01
Author: sstwcw <f0gukp2nk at protonmail.com>
Date: 2022-06-26 (Sun, 26 Jun 2022)
Changed paths:
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
Log Message:
-----------
[clang-format] Fix whitespace counting stuff
The current way of counting whitespace would count backticks as
whitespace. For Verilog stuff we need backticks to be handled
correctly. For JavaScript the current way is to compare the entire
token text to see if it's a backtick. However, when the backtick is the
first token following an escaped newline, the escaped newline will be
part of the tok::unknown token. Verilog has macros and escaped newlines
unlike JavaScript. So we can't regard an entire tok::unknown token as
whitespace. Previously, the start of every token would be matched for
newlines. Now, it is all whitespace instead of just newlines.
The column counting problem has already been fixed for JavaScript in
e71b4cbdd140f059667f84464bd0ac0ebc348387 by counting columns elsewhere.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D124748
Commit: 9ed2e68c9ae5cf346f938cc095e5448c1ff60f51
https://github.com/llvm/llvm-project/commit/9ed2e68c9ae5cf346f938cc095e5448c1ff60f51
Author: sstwcw <f0gukp2nk at protonmail.com>
Date: 2022-06-26 (Sun, 26 Jun 2022)
Changed paths:
M clang/docs/ClangFormat.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/Format.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/tools/clang-format/ClangFormat.cpp
M clang/unittests/Format/CMakeLists.txt
M clang/unittests/Format/FormatTestUtils.h
A clang/unittests/Format/FormatTestVerilog.cpp
Log Message:
-----------
[clang-format] Parse Verilog if statements
This patch mainly handles treating `begin` as block openers.
While and for statements will be handled in another patch.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D123450
Commit: 2e32ff106e740c76601004493816d0ed7c483056
https://github.com/llvm/llvm-project/commit/2e32ff106e740c76601004493816d0ed7c483056
Author: sstwcw <f0gukp2nk at protonmail.com>
Date: 2022-06-26 (Sun, 26 Jun 2022)
Changed paths:
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/FormatTestVerilog.cpp
Log Message:
-----------
[clang-format] Handle Verilog preprocessor directives
Verilog uses the backtick instead of the hash. In this revision
backticks are lexed manually and then get labeled as hashes so the logic
for handling C preprocessor stuff don't have to change. Hashes get
labeled as identifiers for Verilog-specific stuff like delays.
Reviewed By: HazardyKnusperkeks
Differential Revision: https://reviews.llvm.org/D124749
Compare: https://github.com/llvm/llvm-project/compare/b2cb7e81f897...2e32ff106e74
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