[all-commits] [llvm/llvm-project] e01353: [RISCV] Add RISCVISD opcode for PseudoAddTPRel.

Craig Topper via All-commits all-commits at lists.llvm.org
Mon Jun 20 21:05:10 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e01353f816999c92f41168d803af3029792663bc
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td

  Log Message:
  [RISCV] Add RISCVISD opcode for PseudoAddTPRel.

Use it along with RISCVISD::HI and ADD_LO to avoid emitting
MachineSDNodes during lowering.

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