[all-commits] [llvm/llvm-project] 59cde2: Recommit "[RISCV] Enable subregister liveness trac...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 59cde2133d8f2488171404c3e1a8fc302f0249c3
      https://github.com/llvm/llvm-project/commit/59cde2133d8f2488171404c3e1a8fc302f0249c3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-06-20 (Mon, 20 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
    M llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-segN-load.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vector-trunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
    M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
    M llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptrunc-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vlsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vssseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
    M llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll
    M llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll

  Log Message:
  -----------
  Recommit "[RISCV] Enable subregister liveness tracking for RVV."

The failure that caused the previous revert has been fixed
by https://reviews.llvm.org/D126048

Original commit message:

RVV makes heavy use of subregisters due to LMUL>1 and segment
load/store tuples. Enabling subregister liveness tracking improves the quality
of the register allocation.

I've added a command line that can be used to turn it off if it causes compile
time or functional issues. I used the command line to keep the old behavior
for one interesting test case that was testing register allocation.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D128016