[all-commits] [llvm/llvm-project] 8d9d8f: [RISCV] Define risc-v's own register class to mode...

[yanming123456 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 8d9d8f866a16705f47060d986ff5fdbd5c3abc7e
      https://github.com/llvm/llvm-project/commit/8d9d8f866a16705f47060d986ff5fdbd5c3abc7e
  Author: yanming <ming.yan at terapines.com>
  Date:   2022-06-06 (Mon, 06 Jun 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
    M llvm/test/Transforms/LoopVectorize/RISCV/reg-usage.ll

  Log Message:
  -----------
  [RISCV] Define risc-v's own register class to model FP Register.

The default RegisterClass is not enough to model RISCV Register.
We define risc-v's own register class to model FP Register.
This helps to better estimate the register pressure in the loop-vectorize.

Reviewed By: kito-cheng

Differential Revision: https://reviews.llvm.org/D126854