[all-commits] [llvm/llvm-project] 572fc7: [AArch64] Order STP Q's by ascending address

[Andre Vieira via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 572fc7d2fd14b768b58e697015b18c46cafb421c
      https://github.com/llvm/llvm-project/commit/572fc7d2fd14b768b58e697015b18c46cafb421c
  Author: Andre Vieira <andre.simoesdiasvieira at arm.com>
  Date:   2022-05-23 (Mon, 23 May 2022)

  Changed paths:
    A llvm/lib/Target/AArch64/AArch64MachineScheduler.cpp
    A llvm/lib/Target/AArch64/AArch64MachineScheduler.h
    M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
    M llvm/lib/Target/AArch64/CMakeLists.txt
    M llvm/test/CodeGen/AArch64/GlobalISel/call-translator-variadic-musttail.ll
    M llvm/test/CodeGen/AArch64/argument-blocks-array-of-struct.ll
    M llvm/test/CodeGen/AArch64/arm64-memset-inline.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AArch64/sve-fixed-length-fp-select.ll
    M llvm/utils/gn/secondary/llvm/lib/Target/AArch64/BUILD.gn

  Log Message:
  -----------
  [AArch64] Order STP Q's by ascending address

This patch adds an AArch64 specific PostRA MachineScheduler to try to schedule
STP Q's to the same base-address in ascending order of offsets. We have found
this to improve performance on Neoverse N1 and should not hurt other AArch64
cores.

Differential Revision: https://reviews.llvm.org/D125377