[all-commits] [llvm/llvm-project] 534ea8: [AArch64] Generate AND in place of CSEL for predic...

[Rahul via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 534ea8bca51d9e2673a7170c34f1d91b17fabda2
      https://github.com/llvm/llvm-project/commit/534ea8bca51d9e2673a7170c34f1d91b17fabda2
  Author: Rahul Anand R <rahul at rrlogic.co.in>
  Date:   2022-05-20 (Fri, 20 May 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/fold-csel-cttz-and.ll

  Log Message:
  -----------
  [AArch64] Generate AND in place of CSEL for predicated CTTZ

This patch implements a for a target specific optimization that replaces
the cmp and csel from cttz with an and mask.

Recommitted with a fix for truncated value sizes.

Differential Revision: https://reviews.llvm.org/D123782