[all-commits] [llvm/llvm-project] 4c6a07: [AArch64] Teach perfect shuffles tables about D-la...

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c6a070a2ce1722f53da8164b6d50d5d54fdc1d2
      https://github.com/llvm/llvm-project/commit/4c6a070a2ce1722f53da8164b6d50d5d54fdc1d2
  Author: David Green <david.green at arm.com>
  Date:   2022-05-17 (Tue, 17 May 2022)

  Changed paths:
    M clang/test/CodeGen/aarch64-neon-vcmla.c
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    M llvm/lib/Target/AArch64/AArch64PerfectShuffle.h
    M llvm/test/Analysis/CostModel/AArch64/shuffle-other.ll
    M llvm/test/CodeGen/AArch64/arm64-dup.ll
    M llvm/test/CodeGen/AArch64/reduce-shuffle.ll
    M llvm/test/CodeGen/AArch64/shuffle-tbl34.ll
    M llvm/test/CodeGen/AArch64/shuffles.ll
    M llvm/test/Transforms/VectorCombine/AArch64/vecreduce-shuffle.ll
    M llvm/utils/PerfectShuffle/PerfectShuffle.cpp

  Log Message:
  -----------
  [AArch64] Teach perfect shuffles tables about D-lane movs

Similar to D123386, this adds D-Movs to the AArch64 perfect shuffle
tables, slightly lowering the costs a little more. This is a rough
improvement in general, especially if you ignore mov v0.16b, v2.16b type
moves that are often artefacts of the calling convention.

The D register movs are encoded as (0x4 | LaneIdx), and to generate a D
register move we are required to bitcast into a higher type, but it is
otherwise very similar to the S-lane mov's already supported.

Differential Revision: https://reviews.llvm.org/D125477