[all-commits] [llvm/llvm-project] 078174: [RISCV] Add a DAG combine to pre-promote (i32 (and...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 078174278574761edfd557908af59c67aa7b303e
      https://github.com/llvm/llvm-project/commit/078174278574761edfd557908af59c67aa7b303e
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-05-11 (Wed, 11 May 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rv64zbs.ll

  Log Message:
  -----------
  [RISCV] Add a DAG combine to pre-promote (i32 (and (srl X, Y), 1)) with Zbs on RV64.

Type legalization will want to turn (srl X, Y) into RISCVISD::SRLW,
which will prevent us from using a BEXT instruction.

I don't think there is any precedent for type promotion checking
users to decide how to promote. Instead, I've added this DAG combine to
do it before type legalization.

Reviewed By: asb

Differential Revision: https://reviews.llvm.org/D124109