[all-commits] [llvm/llvm-project] f10a8f: [LegalizeDAG] Fix TypeSize conversion error when e...

[paulwalker-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f10a8f675285177d4d720ace0dcdb6a8e714b888
      https://github.com/llvm/llvm-project/commit/f10a8f675285177d4d720ace0dcdb6a8e714b888
  Author: Paul Walker <paul.walker at arm.com>
  Date:   2022-04-30 (Sat, 30 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
    M llvm/test/CodeGen/AArch64/sve-sext-zext.ll

  Log Message:
  -----------
  [LegalizeDAG] Fix TypeSize conversion error when expanding SIGN_EXTEND_INREG

SIGN_EXTEND_INREG expansion can trigger a TypeSize error because
"VT.getSizeInBits() == 1" is used to detect for a boolean without
first verifying VT is a scalar.