[all-commits] [llvm/llvm-project] 808c33: [RISCV][AArch64] Pre-commit tests for D124711. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 808c33ace547f0c71fd256e94fedf879f5e89728
      https://github.com/llvm/llvm-project/commit/808c33ace547f0c71fd256e94fedf879f5e89728
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-30 (Sat, 30 Apr 2022)

  Changed paths:
    A llvm/test/CodeGen/AArch64/pr55201.ll
    A llvm/test/CodeGen/RISCV/pr55201.ll

  Log Message:
  -----------
  [RISCV][AArch64] Pre-commit tests for D124711. NFC


  Commit: 6affe87bda203b6d6538f41bb44879509962c695
      https://github.com/llvm/llvm-project/commit/6affe87bda203b6d6538f41bb44879509962c695
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-04-30 (Sat, 30 Apr 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/pr55201.ll
    M llvm/test/CodeGen/RISCV/pr55201.ll

  Log Message:
  -----------
  [DAGCombiner] When matching a disguised rotate by constant don't forget to apply LHSMask/RHSMask.

We try to match as a disguised rotate by constant of these forms
(shl (X | Y), C1) | (srl X, C2) --> (rotl X, C1) | (shl Y, C1)
(shl X, C1) | (srl (X | Y), C2) --> (rotl X, C1) | (srl Y, C2)

We may have also looked through an AND to find the shift. If we
did, we need to apply a mask to the result.

I'll add an AArch64 test and pre-commit it and the RISC-V test
tomorrow.

Fixes PR55201.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D124711


Compare: https://github.com/llvm/llvm-project/compare/786954db06ab...6affe87bda20