[all-commits] [llvm/llvm-project] 53f3f2: AArch64: Use Register

[Matt Arsenault via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 53f3f2bbb15fb164db820e613be7a22560aa8ffe
      https://github.com/llvm/llvm-project/commit/53f3f2bbb15fb164db820e613be7a22560aa8ffe
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h

  Log Message:
  -----------
  AArch64: Use Register


  Commit: e0d585d75a9ea4af42370d79c7af5aa52d3cfbc8
      https://github.com/llvm/llvm-project/commit/e0d585d75a9ea4af42370d79c7af5aa52d3cfbc8
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
    M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
    M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll

  Log Message:
  -----------
  AMDGPU: Defer creation of WWM VGPR spill slots

There's no reason to create these immediately. They can be created in
the prolog/epilog code like CSR spills. There's probably a cleaner way
to do this by utilizing the CSR spill code.

This makes the frame index used transient state for
PrologEpilogInserter, and thus makes serialization easier. Really this
doesn't need to be saved here but there isn't really a better place
for it.


  Commit: 209e7ef8740838479b79c5b8dfe4d0a820e1e2f0
      https://github.com/llvm/llvm-project/commit/209e7ef8740838479b79c5b8dfe4d0a820e1e2f0
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86MachineFunctionInfo.h

  Log Message:
  -----------
  X86: Do not use ValueMap for PreallocatedIds

ValueMap should only be necessary if the IR values can be
replaced. This is only used during codegen, when it's illegal to
change the underlying IR. This allows using the default copy
constructor for X86MachineFunctionInfo.

I'm not happy about targets keeping state here that's only used in one
specific pass, but we don't have a better place to put it right now.


  Commit: 9a519179d9efcde3eb8e1808258de1f0d637e990
      https://github.com/llvm/llvm-project/commit/9a519179d9efcde3eb8e1808258de1f0d637e990
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/include/llvm/IR/ValueMap.h

  Log Message:
  -----------
  ValueMap: Fix typo


  Commit: 9592e88f59cfd399e9285cfec50a23675f43a43a
      https://github.com/llvm/llvm-project/commit/9592e88f59cfd399e9285cfec50a23675f43a43a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineModuleInfo.h
    M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
    M llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp
    M llvm/lib/CodeGen/MachineModuleInfo.cpp
    A llvm/test/CodeGen/X86/disable-debug-info-print-codeview.ll
    A llvm/test/DebugInfo/COFF/emission-kind-no-debug.ll
    M llvm/test/DebugInfo/COFF/language.ll

  Log Message:
  -----------
  MachineModuleInfo: Don't allow dynamically setting DbgInfoAvailable

This can be set up front, and used only as a cache. This avoids a
field that looks like it requires MIR serialization.

I believe this fixes 2 bugs for CodeView. First, this addresses a
FIXME that the flag -diable-debug-info-print only works with
DWARF. Second, it fixes emitting debug info with emissionKind NoDebug.


Compare: https://github.com/llvm/llvm-project/compare/4271ae22bedd...9592e88f59cf