[all-commits] [llvm/llvm-project] 96c919: AArch64/GlobalISel: Remove asserts on copy instruc...

Tue Apr 19 18:04:45 PDT 2022

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 96c9190761af0e278bfd7a00738c856b23748588
      https://github.com/llvm/llvm-project/commit/96c9190761af0e278bfd7a00738c856b23748588
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

  Log Message:
  -----------
  AArch64/GlobalISel: Remove asserts on copy instructions

These things are checked in the verifier already, so there's not much
point in re-asserting them here. They aren't directly verified for the
copy-like extension artifacts, but the incorrect output copies would
be caught on the other side.

  Commit: e38c5fded6dbff07d3ae961c32be3a3d5dfd045a
      https://github.com/llvm/llvm-project/commit/e38c5fded6dbff07d3ae961c32be3a3d5dfd045a
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

  Log Message:
  -----------
  AArch64/GlobalISel: Remove some null checks for getVRegDef

getVRegDef is not allowed to fail for generic virtual registers, so
there's not much point in checking it.

  Commit: 12d79b1514b8036a6079495a45091c9bfb8db1a6
      https://github.com/llvm/llvm-project/commit/12d79b1514b8036a6079495a45091c9bfb8db1a6
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/include/llvm/Support/LowLevelTypeImpl.h
    M llvm/include/llvm/Support/TypeSize.h
    M llvm/unittests/CodeGen/LowLevelTypeTest.cpp

  Log Message:
  -----------
  GlobalISel: Add LLT helper to multiply vector sizes

  Commit: d6457ec04af3f6e6cec7c8f228a1f6908363a944
      https://github.com/llvm/llvm-project/commit/d6457ec04af3f6e6cec7c8f228a1f6908363a944
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

  Log Message:
  -----------
  AArch64/GlobalISel: Reduce use of getMinClassForRegBank

getMinClassForRegBank and getRegClassForTypeOnBank were basically
identical functions with different APIs. Consolidate on the version
that uses LLT instead of a bitwidth, since that would be more
appropriate to use in a generic API. Keep getMinClassForRegBank around
for now, since copies are a special case that can't simply read the
type from the register operands.

  Commit: 507259820aa4a6892585d5435c7459fa13a729c1
      https://github.com/llvm/llvm-project/commit/507259820aa4a6892585d5435c7459fa13a729c1
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
    M llvm/lib/CodeGen/GlobalISel/LegalizeMutations.cpp
    M llvm/unittests/CodeGen/GlobalISel/LegalizerInfoTest.cpp

  Log Message:
  -----------
  GlobalISel: Add LegalizeMutations to help use More/FewerElements

  Commit: d16945d31b1f74f460d54b538101e7e9fe24680c
      https://github.com/llvm/llvm-project/commit/d16945d31b1f74f460d54b538101e7e9fe24680c
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-brcond-fcmp.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-fp-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fold-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-and-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-ext-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-shift-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-trunc-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-xor-tbz-tbnz.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/preselect-process-phis.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-jump-table-brjt.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-saddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ssubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-trunc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-uaddo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-usubo.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/speculative-hardening-brcond.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/widen-narrow-tbz-tbnz.mir

  Log Message:
  -----------
  AArch64/GlobalISel: Add -global-isel-abort=1 to select tests

Otherwise the legalizer verifier error isn't triggered since the
default is fallback.

  Commit: 8591328e15940c5b36d30954fdcc065597dc0d76
      https://github.com/llvm/llvm-project/commit/8591328e15940c5b36d30954fdcc065597dc0d76
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/include/llvm/IR/Intrinsics.td
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
    M llvm/test/Verifier/intrinsic-immarg.ll

  Log Message:
  -----------
  Intrinsics: Mark llvm.eh.sjlj.callsite argument as immarg

The assert in SelectionDAG implies that it is

  Commit: bc7902f1483c20dd1bf78f7115b3e9c59f8e01cc
      https://github.com/llvm/llvm-project/commit/bc7902f1483c20dd1bf78f7115b3e9c59f8e01cc
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
    M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h

  Log Message:
  -----------
  AMDGPU: Remove unused MachineFunctionInfo fields

These were leftovers from a half-implement spill to LDS attempt.

  Commit: 4271ae22beddac33e7cdb1e48002a82f9e2e5684
      https://github.com/llvm/llvm-project/commit/4271ae22beddac33e7cdb1e48002a82f9e2e5684
  Author: Matt Arsenault <Matthew.Arsenault at amd.com>
  Date:   2022-04-19 (Tue, 19 Apr 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp

  Log Message:
  -----------
  AMDGPU: Remove some unreachable code in WWM pass

Defs must be registers and there's no point to code after
llvm_unreachable.

Compare: https://github.com/llvm/llvm-project/compare/c129220eaa98...4271ae22bedd