[all-commits] [llvm/llvm-project] 18106b: [VP] Explicitly map from VP intrinsic to ISD opcode

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 18106b99f0c3076220e86123d1c19e0d38683b60
      https://github.com/llvm/llvm-project/commit/18106b99f0c3076220e86123d1c19e0d38683b60
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2022-04-08 (Fri, 08 Apr 2022)

  Changed paths:
    M llvm/include/llvm/IR/VPIntrinsics.def
    M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

  Log Message:
  -----------
  [VP] Explicitly map from VP intrinsic to ISD opcode

This patch aims to overcome an issue in these mappings where, when an ISD
node was registered with BEGIN_REGISTER_VP_SDNODE but outwidth the scope
of a pair of BEGIN_REGISTER_VP_INTRINSIC/END_REGISTER_VP_INTRINSIC
macros, the switch cases fell apart. This in particular happened with
VP_SETCC, where we'd end up with something along the lines of:

  case Intrinsic::vp_fcmp:
    break;
  case Intrinsic::vp_icmp:
    break;
    ResOpc = ISD::VP_SETCC;
  case Intrinsic::vp_store:
    ...

To remedy this, we introduce a special-purpose mapping macro which can
map any number of VP intrinsic opcodes to an ISD opcode.

As a result, we no longer need to special-case the mapping from vp.icmp
and vp.fcmp to VP_SETCC, as the new helper macro does it for us.

Thanks to @craig.topper for noticing this and to @rogfer01 for the idea.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D123324