[all-commits] [llvm/llvm-project] 9b0f22: [TableGen][RISCV] Add InstAliases with zero_reg to...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9b0f227d7b2cee4e4492d0501e032f9b33579853
      https://github.com/llvm/llvm-project/commit/9b0f227d7b2cee4e4492d0501e032f9b33579853
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-22 (Tue, 22 Mar 2022)

  Changed paths:
    M llvm/lib/Target/ARM/ARMInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
    M llvm/test/CodeGen/RISCV/rvv/aliases.mir
    M llvm/test/CodeGen/RISCV/rvv/constant-folding.ll
    M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extload-truncstore.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-exttrunc.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpgather.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpscatter.ll
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/legalize-scalable-vectortype.ll
    M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/mscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfabs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vfneg-vp.ll
    M llvm/test/CodeGen/RISCV/rvv/vfptoi-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpgather-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vpscatter-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
    M llvm/test/CodeGen/RISCV/rvv/vtruncs-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll
    M llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll
    M llvm/test/MC/RISCV/rvv/add.s
    M llvm/test/MC/RISCV/rvv/xor.s
    M llvm/utils/TableGen/AsmWriterEmitter.cpp

  Log Message:
  -----------
  [TableGen][RISCV] Add InstAliases with zero_reg to cover unmasked vnot.v, vncvt.x.x.w, vneg.v, etc.

The mask being NoRegister prevented the existing aliases from matching
since NoRegister isn't in the VMV0 register class.

To workaround this I've added new aliases that look for zero_reg.
I had to motify tablegen to generate matching code for zero_reg.
And as a consequence, I had to change the EmitPriority for an ARM
alias that used zero_reg that started printing.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D121496