[all-commits] [llvm/llvm-project] ad94df: [DAGCombiner][RISCV] Adjust (aext (and (trunc x), ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ad94dfb9a0f6bf1661845c9dd5f436b481a9762a
      https://github.com/llvm/llvm-project/commit/ad94dfb9a0f6bf1661845c9dd5f436b481a9762a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-15 (Tue, 15 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/RISCV/and.ll

  Log Message:
  -----------
  [DAGCombiner][RISCV] Adjust (aext (and (trunc x), cst)) -> (and x, cst) to sext cst based on target preference

RISCV strong prefers i32 values be sign extended to i64. This combine
was always zero extending the constant using APInt methods.

This adjusts the code so that it calls getNode using ISD::ANY_EXTEND instead.
getNode will call TLI.isSExtCheaperThanZExt to decide how to handle
the constant.

Tests were copied from D121598 where I noticed that we were creating
constants that were hard to materialize.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D121650