[all-commits] [llvm/llvm-project] 9f4caf: [AArch64] add tests for bitwise logic reassociatio...

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 9f4caf55dba417d4d67526d7bc8f23a12090bca9
      https://github.com/llvm/llvm-project/commit/9f4caf55dba417d4d67526d7bc8f23a12090bca9
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-03-13 (Sun, 13 Mar 2022)

  Changed paths:
    A llvm/test/CodeGen/AArch64/logic-reassociate.ll

  Log Message:
  -----------
  [AArch64] add tests for bitwise logic reassociation; NFC

Chooses from a variety of scalar/vector/illegal types
because that should not inhibit any folds.


  Commit: c2592c374e469f343ecea82d6728609650924259
      https://github.com/llvm/llvm-project/commit/c2592c374e469f343ecea82d6728609650924259
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-03-13 (Sun, 13 Mar 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/logic-reassociate.ll
    M llvm/test/CodeGen/VE/Scalar/max.ll
    M llvm/test/CodeGen/X86/legalize-shift.ll
    M llvm/test/CodeGen/X86/pr32345.ll
    M llvm/test/CodeGen/X86/pr34137.ll
    M llvm/test/CodeGen/X86/urem-seteq.ll

  Log Message:
  -----------
  [SDAG] simplify bitwise logic with repeated operand

We do not have general reassociation here (and probably
do not need it), but I noticed these were missing in
patches/tests motivated by D111530, so we can at
least handle the simplest patterns.

The VE test diff looks correct, but we miss that
pattern in IR currently:
https://alive2.llvm.org/ce/z/u66_PM


Compare: https://github.com/llvm/llvm-project/compare/1a5a2b3d37d9...c2592c374e46