[all-commits] [llvm/llvm-project] b55a77: [RISCV] Add Zbp command lines to bswap-bitreverse....

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b55a77d2229d5e2d355a14a537fd6c98607021de
      https://github.com/llvm/llvm-project/commit/b55a77d2229d5e2d355a14a537fd6c98607021de
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-12 (Sat, 12 Mar 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

  Log Message:
  -----------
  [RISCV] Add Zbp command lines to bswap-bitreverse.ll. NFC


  Commit: fd4d584d6b5c8c1e8d4fd9cbf171247f72fa9b21
      https://github.com/llvm/llvm-project/commit/fd4d584d6b5c8c1e8d4fd9cbf171247f72fa9b21
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-12 (Sat, 12 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/bswap-bitreverse.ll

  Log Message:
  -----------
  [RISCV] Add DAGCombine to fold (bitreverse (bswap X)) to brev8 with Zbkb.

If the type is less than XLenVT, type legalization will turn this
into (srl (bitreverse (bswap (srl (bswap X), C))), C). We can't
completely recover from these shifts. They introduce zeros into
the upper bits of the result and we can't easily tell if they are
needed. By doing a DAG combine early, we avoid introducing these
shifts.


Compare: https://github.com/llvm/llvm-project/compare/e3550f1903d2...fd4d584d6b5c