[all-commits] [llvm/llvm-project] aeeb11: [AArch64][SVE] Change the asserts in LowerToPredic...

[david-arm via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: aeeb1199b4b4d33b823bae15ca969527c89676cf
      https://github.com/llvm/llvm-project/commit/aeeb1199b4b4d33b823bae15ca969527c89676cf
  Author: David Sherwood <david.sherwood at arm.com>
  Date:   2022-03-11 (Fri, 11 Mar 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    A llvm/test/CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll

  Log Message:
  -----------
  [AArch64][SVE] Change the asserts in LowerToPredicatedOp to check for legal types

When building the LLVM test suite with SVE I discovered a crash
when compiling some Halide tests, which occurs because we try to
use SVE to lower 64-bit vector multiplies and there is no
vscale_range attribute on the function. In this case the min SVE
vector bits was 0, which caused an assert in LowerToPredicatedOp
to fire. I have amended the asserts in this function to check that the
fixed-width type is legal. If the fixed-width type is larger than NEON
and is legal then it must be because we've set the min SVE vector
bits to something > 128. Or if the min SVE bits is 0, then the only
legal types allowed are 128 bit types - for any other types the assert
will fire.

Tests added here:

  CodeGen/AArch64/sve-fixed-length-no-vscale-range.ll

Differential Revision: https://reviews.llvm.org/D121297