[all-commits] [llvm/llvm-project] e0e8ed: [RISCV] Add isel patterns for masked RISCVISD::FMA...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: e0e8edf82327ca16eceead3e5c22fb7a78d9998d
      https://github.com/llvm/llvm-project/commit/e0e8edf82327ca16eceead3e5c22fb7a78d9998d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-10 (Thu, 10 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
    M llvm/test/CodeGen/RISCV/rvv/vfma-vp.ll

  Log Message:
  -----------
  [RISCV] Add isel patterns for masked RISCVISD::FMA_VL with RISCVISD::FNEG_VL.

This helps us form vfnmsub, vfnmadd, and vfmusb from masked VP
intrinsics.

I've used "srcvalue" for the mask parameter in the fneg nodes. We
can't match "V0" because that doesn't ensure the mask the is the same.
Instead it matches two different nodes and generates two copies to
V0 of those separate values.

Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D120287