[all-commits] [llvm/llvm-project] edd663: [RISCV] Support 'generic' as a valid CPU name.

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: edd6632127975c61181dc8003c1271d4d86255b1
      https://github.com/llvm/llvm-project/commit/edd6632127975c61181dc8003c1271d4d86255b1
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-03-09 (Wed, 09 Mar 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVSubtarget.cpp

  Log Message:
  -----------
  [RISCV] Support 'generic' as a valid CPU name.

Most other targets support 'generic', but RISCV issues an error.
This can require a special case in tools that use LLVM that aren't
clang.

This patch treats "generic" the same as an empty string and remaps
it to generic-rv/rv64 based on the triple. Unfortunately, it has to
be added to RISCV.td because MCSubtargetInfo is constructed and
parses the CPU before RISCVSubtarget's constructor gets a chance
to remap it. The CPU will then reparsed and the state in the
MCSubtargetInfo subclass will be updated again.

Fixes PR54146.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D121149