[all-commits] [llvm/llvm-project] 2f80ea: [NFC][LV] Use different braces in debug output

[Roman Lebedev via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2f80ea7f4f7e93c57af30c2243082bb8c817052b
      https://github.com/llvm/llvm-project/commit/2f80ea7f4f7e93c57af30c2243082bb8c817052b
  Author: Roman Lebedev <lebedev.ri at gmail.com>
  Date:   2022-03-07 (Mon, 07 Mar 2022)

  Changed paths:
    M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
    M llvm/test/Analysis/CostModel/X86/gather-i16-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/gather-i32-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/gather-i64-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/gather-i8-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2-indices-0u.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-01u.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3-indices-0uu.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-012u.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-01uu.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4-indices-0uuu.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f32-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-f64-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-5.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i32-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i64-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-2.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-3.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-4.ll
    M llvm/test/Analysis/CostModel/X86/interleaved-store-i8-stride-6.ll
    M llvm/test/Analysis/CostModel/X86/masked-gather-i32-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/masked-gather-i64-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/masked-interleaved-load-i16.ll
    M llvm/test/Analysis/CostModel/X86/masked-interleaved-store-i16.ll
    M llvm/test/Analysis/CostModel/X86/masked-load-i16.ll
    M llvm/test/Analysis/CostModel/X86/masked-load-i32.ll
    M llvm/test/Analysis/CostModel/X86/masked-load-i64.ll
    M llvm/test/Analysis/CostModel/X86/masked-load-i8.ll
    M llvm/test/Analysis/CostModel/X86/masked-scatter-i32-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/masked-scatter-i64-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/masked-store-i16.ll
    M llvm/test/Analysis/CostModel/X86/masked-store-i32.ll
    M llvm/test/Analysis/CostModel/X86/masked-store-i64.ll
    M llvm/test/Analysis/CostModel/X86/masked-store-i8.ll
    M llvm/test/Analysis/CostModel/X86/scatter-i16-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/scatter-i32-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/scatter-i64-with-i8-index.ll
    M llvm/test/Analysis/CostModel/X86/scatter-i8-with-i8-index.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/interleaved_cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/masked-op-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vectorization.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/scalable-vf-hint.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/smallest-and-widest-types.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vect.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-gather-scatter-cost.ll
    M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-gep.ll
    M llvm/test/Transforms/LoopVectorize/ARM/arm-ieee-vectorize.ll
    M llvm/test/Transforms/LoopVectorize/ARM/interleaved_cost.ll
    M llvm/test/Transforms/LoopVectorize/ARM/mve-interleaved-cost.ll
    M llvm/test/Transforms/LoopVectorize/SystemZ/mem-interleaving-costs-02.ll
    M llvm/test/Transforms/LoopVectorize/X86/already-vectorized.ll
    M llvm/test/Transforms/LoopVectorize/X86/reg-usage-debug.ll
    M llvm/test/Transforms/LoopVectorize/X86/uniformshift.ll
    M llvm/test/Transforms/LoopVectorize/X86/vector-scalar-select-cost.ll
    M llvm/test/Transforms/LoopVectorize/icmp-uniforms.ll
    M llvm/test/Transforms/LoopVectorize/interleaved-accesses-masked-group.ll
    M llvm/test/Transforms/LoopVectorize/loop-legality-checks.ll
    M llvm/test/Transforms/LoopVectorize/nounroll.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-limitations.ll
    M llvm/test/Transforms/LoopVectorize/optimal-epilog-vectorization-scalable.ll
    M llvm/test/Transforms/LoopVectorize/pr39099.ll
    M llvm/test/Transforms/LoopVectorize/vect.omp.persistence.ll
    M llvm/test/Transforms/LoopVectorize/vplan-printing.ll
    M llvm/test/Transforms/LoopVectorize/vplan-sink-scalars-and-merge.ll

  Log Message:
  -----------
  [NFC][LV] Use different braces in debug output

The analysis passes output function name encapsulated in `'` braces,
but LV uses `"`. Harmonizing this may help in creating an update script
for the LV costmodel test checks.

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D121105