[all-commits] [llvm/llvm-project] 2b4641: [X86][SSE] Attempt to lower vec_reduce_add pattern...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 2b46417aa2d42d5d2a14df1675cfee547fd46556
      https://github.com/llvm/llvm-project/commit/2b46417aa2d42d5d2a14df1675cfee547fd46556
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2022-02-27 (Sun, 27 Feb 2022)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
    M llvm/test/CodeGen/X86/vector-reduce-add-zext.ll

  Log Message:
  -----------
  [X86][SSE] Attempt to lower vec_reduce_add patterns with PSADBW for zero-extended vXi8 sources

For i16/32/64 vectors, if the upper bits are known to be zero, then we can try to truncate to vXi8 (if its worth it) and perform this as a PSADBW to add+zext each v4i8 subvector to a i64 sum, which we can then reduce together.

This addresses some of the PR42674 test cases where the source data was vXi8 but had been extended to match a wider unsigned integer accumulator.

Differential Revision: https://reviews.llvm.org/D120193