[all-commits] [llvm/llvm-project] acb96f: [SDAG] fold bitwise logic with shifted operands

[Sanjay Patel via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: acb96ffd149db447b78d3ab33fbc9f93ce781c46
      https://github.com/llvm/llvm-project/commit/acb96ffd149db447b78d3ab33fbc9f93ce781c46
  Author: Sanjay Patel <spatel at rotateright.com>
  Date:   2022-02-27 (Sun, 27 Feb 2022)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/AArch64/icmp-shift-opt.ll
    M llvm/test/CodeGen/AArch64/logic-shift.ll
    M llvm/test/CodeGen/ARM/consthoist-icmpimm.ll
    M llvm/test/CodeGen/ARM/icmp-shift-opt.ll
    M llvm/test/CodeGen/X86/icmp-shift-opt.ll
    M llvm/test/CodeGen/X86/logic-shift.ll

  Log Message:
  -----------
  [SDAG] fold bitwise logic with shifted operands

LOGIC (LOGIC (SH X0, Y), Z), (SH X1, Y) --> LOGIC (SH (LOGIC X0, X1), Y), Z

https://alive2.llvm.org/ce/z/QmR9rR

This is a reassociation + factoring fold. The common shift operation is moved
after a bitwise logic op on 2 input operands.
We get simpler cases of these patterns in IR, but I suspect we would miss all
of these exact tests in IR too. We also handle the simpler form of this plus
several other folds in DAGCombiner::hoistLogicOpWithSameOpcodeHands().

This is a partial implementation of a transform suggested in D111530
(only handles 'or' bitwise logic as a first step - need to stamp out more
tests for other opcodes).
Several of the same tests added for D111530 are altered here (but not
fully optimized). I'm not sure yet if this would help/hinder that patch,
but this should be an improvement for all tests added with ecf606cb4329ae
since it removes a shift operation in those examples.

Differential Revision: https://reviews.llvm.org/D120516