[all-commits] [llvm/llvm-project] ba9a7a: [RISCV] Add test case for a vsetvli insertion bug ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ba9a7ae798053d7cf741143739351b5a4ac29d8b
      https://github.com/llvm/llvm-project/commit/ba9a7ae798053d7cf741143739351b5a4ac29d8b
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-11 (Fri, 11 Feb 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Add test case for a vsetvli insertion bug found after D118667.

We're missing a vsetvli before a vse after a redsum in this test.

This appears to be because the vmv.s.x has a VL of 1, but did not
trigger a vsetvli because it is a scalar move op and any non-zero
VL would work. So it looked at it the predecessors and decided it was
that they all had a non-zero vl. Then the redsum was visited, it
also took the VL from the predecessors since the vmv.s.x and the 4
was found compatible.

Finally we visit the vse and it looks at the BBLocalInfo and sees
that is compatible because it contains a VL of 1 from the vmv.s.x,
the first instruction in the block. BBLocalInfo was not updated
when the vredsum was visited because BBLocalInfo was valid and no
vsetvli was generated.

I think fundamentally the vmv.s.x optimization has the same first
phase and third phase not matching problem that D118667 was trying
to fix for stores.

Differential Revision: https://reviews.llvm.org/D119516


  Commit: f35ac872b8224f771808a9ecd5c4da0fe307ac9c
      https://github.com/llvm/llvm-project/commit/f35ac872b8224f771808a9ecd5c4da0fe307ac9c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-11 (Fri, 11 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  Revert "[RISCV] Fix a vsetvli insertion bug involving loads/stores." and "[RISCC] Add missing words to comment. NFC"

This reverts commit f943c58cae2480755cecdac5be832274f238df93.
and commit 7eb781072744b31a60e82b5a5903471032d4845f.

This introduced a new bug that appears to be easier to hit.

Differential Revision: https://reviews.llvm.org/D119517


  Commit: 541c9ba842256023611e5a6c5f01e01c40688044
      https://github.com/llvm/llvm-project/commit/541c9ba842256023611e5a6c5f01e01c40688044
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2022-02-11 (Fri, 11 Feb 2022)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Insert VSETVLI at the end of a basic block if we didn't produce BlockInfo.Exit.

This is an alternative to D118667 that instead of fixing the store
to match phase 1, it tries to detect the mismatch with the expected
value at the end of the block. This inserts a vsetvli after the vse
to satisfy the requirement of the other basic block.

We still have serious design issues in the pass, that is going to
require some rethinking.

Differential Revision: https://reviews.llvm.org/D119518


Compare: https://github.com/llvm/llvm-project/compare/08f2b0dcf61f...541c9ba84225