[all-commits] [llvm/llvm-project] b59ad6: [TableGen][AMDGPU] Allow empty register classes

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b59ad64eadc045f1f69513a9f134de4f35694849
      https://github.com/llvm/llvm-project/commit/b59ad64eadc045f1f69513a9f134de4f35694849
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2022-02-11 (Fri, 11 Feb 2022)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
    M llvm/test/CodeGen/AMDGPU/accvgpr-copy.mir
    M llvm/utils/TableGen/CodeGenRegisters.cpp
    M llvm/utils/TableGen/RegisterInfoEmitter.cpp

  Log Message:
  -----------
  [TableGen][AMDGPU] Allow empty register classes

Remove ARTIFICIAL_VGPR which only existed to make VReg_1 not empty.

Differential Revision: https://reviews.llvm.org/D119552