[all-commits] [llvm/llvm-project] b00bce: [RISCV] Add a test showing an incorrect VSETVLI in...

[Fraser Cormack via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b00bce2a93b3c14379e088225c45a341ad75ba0f
      https://github.com/llvm/llvm-project/commit/b00bce2a93b3c14379e088225c45a341ad75ba0f
  Author: Fraser Cormack <fraser at codeplay.com>
  Date:   2022-02-01 (Tue, 01 Feb 2022)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir

  Log Message:
  -----------
  [RISCV] Add a test showing an incorrect VSETVLI insertion

This test shows a loop, whose preheader uses a SEW=64, LMUL=1 vector
operation. The loop body starts off with another SEW=64, LMUL=1 VADD
vector operation, before switching to a SEW=32, LMUL=1/2 vector store
instruction.

We can see that the VSETVLI insertion pass omits a VSETVLI before the
VADD (thinking it inherits its configuration from the preheader) but
does place a SEW=32, LMUL=1/2 VSETVLI before the store. This results in
a miscompilation as when the loop comes back around, the VADD is
incorrectly configured with SEW=32, LMUL=1/2.

It appears to be a bad load/store optimization, as replacing the vector
store with an SEW=32, LMUL=1/2 VADD does correctly insert a VSETVLI. The
issue is therefore possibly arising from canSkipVSETVLIForLoadStore.

Differential Revision: https://reviews.llvm.org/D118629