[all-commits] [llvm/llvm-project] 19b9cd: [MC] Add a disassembly test for Armv8-R sysregs.

[Simon Tatham via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 19b9cd4eae6fd84ff380c9769052522658c950fc
      https://github.com/llvm/llvm-project/commit/19b9cd4eae6fd84ff380c9769052522658c950fc
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2022-01-20 (Thu, 20 Jan 2022)

  Changed paths:
    A llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt

  Log Message:
  -----------
  [MC] Add a disassembly test for Armv8-R sysregs.

This is the counterpart to llvm/test/MC/AArch64/armv8r-sysreg.s,
checking all the same encodings when fed to the disassembler.


  Commit: a4ac40e92f718d487898bd204517c38113afd3bb
      https://github.com/llvm/llvm-project/commit/a4ac40e92f718d487898bd204517c38113afd3bb
  Author: Simon Tatham <simon.tatham at arm.com>
  Date:   2022-01-20 (Thu, 20 Jan 2022)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64SystemOperands.td
    M llvm/test/MC/AArch64/armv8r-sysreg.s
    M llvm/test/MC/Disassembler/AArch64/armv8r-sysreg.txt

  Log Message:
  -----------
  [AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.

The Armv8-R.64 architecture defines numbered MPU region registers with
indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or
PRLAR0_EL1 (for example). The encodings that they would occupy are
used for the unnumbered PRBAR_ELn and PRLAR_ELn registers.

Reviewed By: labrinea

Differential Revision: https://reviews.llvm.org/D117755


Compare: https://github.com/llvm/llvm-project/compare/d8b690409dae...a4ac40e92f71